Recently, techniques for forming a semiconductor layer with a crystal structure (which will be referred to herein as a “crystalline semiconductor layer”) by crystallizing an amorphous semiconductor layer that has been deposited on an insulating substrate such as a glass substrate have been researched extensively. Examples of such crystalline semiconductor layers include polycrystalline semiconductor layers and microcrystalline semiconductor layers. A thin-film transistor (TFT) that has been fabricated with a crystalline semiconductor layer has far higher carrier mobility than a TFT that has been fabricated with an amorphous semiconductor layer. For that reason, pixel TFTs for the display area on an active-matrix substrate with a built-in driver, which can be used effectively in a display device (such as a liquid crystal display device), and driver TFTs for the peripheral area thereof are fabricated using a crystalline semiconductor layer.
As a technique for crystallizing an amorphous semiconductor layer, a continuous grain silicon (CGS) process, in which the amorphous semiconductor layer is heated with a catalyst element (such as nickel) added thereto, is known. According to such a technique, a crystalline semiconductor layer of good quality with aligned crystallographic plane orientations can be obtained in a short time and at a low temperature. However, in a situation where a crystalline semiconductor layer has been formed by the CGS process, if the catalyst element remains in the channel region, then the OFF-state current of TFTs might increase suddenly. To suppress such a sudden increase in OFF-state current, a countermeasure for providing a gettering region to remove the catalyst element by a gettering process is known (see Patent Document No. 1, for example).
FIG. 13 illustrates a semiconductor device 800 as disclosed in Patent Document No. 1. The crystalline semiconductor layer 810 of the semiconductor device 800 has gettering regions 812 and 814 at the ends. Specifically, the gettering region 812 is arranged adjacent to a source region 832 so as to secure an electrical charge path leading from the source region 832 to a channel region 834. The source region 832 contacts with a source electrode 872 at source contact portions 832c, which are arranged around its center. Likewise, the gettering region 814 is arranged adjacent to a drain region 836 so as to secure an electrical charge path leading from the channel region 834 to the drain region 836. The drain region 836 contacts with a drain electrode 882 at drain contact portions 836c, which are arranged around its center. A Group V element such as phosphorus has been introduced into the gettering regions 812 and 814. By moving (i.e., gettering) a catalyst element remaining in the channel region 834 by heating it, the sudden increase in the OFF-state current of TFTs is suppressed.                Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 2006-128469        